1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. For example, isolation regions are used to isolate field effect transistors (FETs) from each other in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide the isolation regions among the various devices in the substrate. However, there are still some drawbacks, such as internal stress generation and bird's beak encroachment, in the LOCOS process. Shallow trench isolation (STI) has become widely used in highly integrated devices because STI is scaleable and has no bird's beak encroachment problem as found in the conventional LOCOS technique.
In the fabrication process of the STI structure, an isolation layer is deposited to fill the trench and then a chemical-mechanical polishing step is performed in order to obtain a planarized surface. However, because self-planarization of the isolation layer is poor, it is easy to obtain surface having a deep step height after chemical-mechanical polishing.
In the conventional method of forming the shallow trench isolation, the surface having a deep step height over the substrate causes dishing in the isolation layer. Because electrons easily gather in the recessed isolation layer, which is arising from dishing, the threshold voltage of devices is decreased and the abnormal sub-threshold current is likely to occur. The aforementioned problem is called a kink effect, which degrades the device quality and decreases the throughput.